Electromechanical micromirror devices have drawn considerable interest because of their application as spatial light modulators (SLMs). A spatial light modulator requires an array of a relatively large number of such micromirror devices. In general, the number of devices required ranges from 60,000 to several million for each SLM. Despite significant advances that have been made in recent years, there is still a need for improvement in the performance and manufacturing yields of electromechanical micromirror devices.
An example of an early generation prior art device is disclosed in U.S. Pat. No. 4,592,628. U.S. Pat. No. 4,592,628 describes an array of light reflecting devices on a substrate. Each device comprises a hollow post and a deflectable polygonal mirror attached thereto. Each mirror acts as a deflectable cantilever beam. The mirrors are deflected by a beam of electrons from a cathode ray tube. FIG. 4 of U.S. Pat. No. 4,592,628 shows the micromirror device enclosed in the evacuated interior of a cathode ray tube.
A 1st generation Texas Instruments, Inc. (TI) device is described in U.S. Pat. No. 4,662,746. A micromirror is suspended by 1 or 2 hinges. If suspended by 1 hinge, the micromirror deflects like a cantilever beam. If suspended by 2 hinges, the micromirror deflects like a torsion beam. Addressing electrodes are located below the micromirrors and addressing circuits are located at the same level in the substrate as the addressing electrodes.
2nd generation TI device is described in U.S. Pat. No. 5,583,688. A 2nd generation TI device is one in which the torsion hinge is at a different level than the reflective mirror. As described more fully in U.S. Pat. No. 5,583,688, the mirror is supported by a mirror support post, which is attached to the torsion hinge by a yoke. In U.S. Pat. No. 5,583,688, the mirrors are actuated by electrostatic forces between the mirror and address electrodes. The device is designed such that the mirror edge do not touch the address electrodes. Instead, the yoke edge touches the yoke landing site. The fill factor is relatively high because the CMOS circuits and torsion hinges are hidden under the mirror. Metallic pads are placed along at least one peripheral edge of the array for making electrical connections. In the conventional art, the electrical connections are made by wire bonding.
Micromirrors that are described in U.S. Pat. No. 4,662,746 and U.S. Pat. No. 5,583,688 are fabricated on top of CMOS circuits. There may be manufacturing problems associated with the fabrication of micromirrors on top of CMOS circuits. This issue is discussed in U.S. Pat. No. 5,216,537. In this patent, it is discussed that the surface of the CMOS chip has certain manufacturing artifacts, namely aluminum hillocks, pinholes, nonplanar surfaces, and steep sidewalls in the protective oxide at edges of aluminum leads. In response to these problems, U.S. Pat. No. 5,216,537 discloses an improved architecture in which an air gap is provided between the top surface of the CMOS chip and the mirror addressing electrodes. A further advantage of this approach is that because of the low dielectric constant of air, parasitic coupling between the CMOS and the micromirror is reduced.
The placement of CMOS circuits directly under the micromirrors is also responsible for problems of photosensitivity. As discussed in U.S. Pat. No. 6,344,672, it was found that the CMOS memory cells are unstable in a high-intensity light environment. The patent provided an active collector region in which photogenerated carriers could recombine before reaching the addressing electrode.
Reflectivity, Inc. (Sunnyvale, Calif.) is also known to be developing micromirror devices. As disclosed in U.S. Pat. No. 5,835,256, the aforementioned problems associated with placing CMOS and micromirrors on the same substrate are solved by placing the micromirrors and CMOS on different substrates. In other words, a hinge and a micromirror are fabricated on an optically transparent substrate, such that the optically reflective surface of the micromirror is proximate the optically transparent substrate. Addressing circuits including mirror addressing electrodes are fabricated on a 2nd substrate (typically silicon) and the 2 substrates are bonded together with a predetermined gap between the micromirror and the addressing electrodes.
However, a difficulty with the architecture of U.S. Pat. No. 5,835,256 is that the gap between the mirror and mirror addressing electrodes is difficult to control. Since the actuation force is superlinearly dependent on this gap, it is imperative to achieve uniform gap over the entire array to obtain uniform performance characteristics. As discussed in US 2003/0134449 A1, 2nd and higher order adjustments in the gap may be needed in the manufacturing process. Such adjustments make the manufacturing process more complicated. It would be preferable to have a device architecture in which the mirror address electrodes and mirrors are disposed on the same substrate.
U.S. Pat. No. 6,538,800 discusses the use of amorphous silicon as a sacrificial layer in fabricating a micromirror device. It is shown that amorphous silicon can be deposited for this purpose by LPCVD in a quartz tube of a Tylan furnace. It is also shown that a xenon difluoride etch process can be used to etch amorphous silicon with a selectivity of 100 to 1. Therefore, amorphous silicon can be used successfully as a sacrificial layer in addition to photoresists, silicon oxide, silicon nitride, and silicon oxynitride.
In many cases, there is a need to encapsulate MEMS devices in a vacuum. There is the example of aforementioned U.S. Pat. No. 4,592,628 in which the micromirror device is encapsulated in the vacuum of a cathode ray tube. U.S. Pat. No. 6,479,320 describes the vacuum packaging of MEMS devices such as infrared bolometers, gyros, and accelerometers. Instead of packaging individual chips, the entire wafer is packaged simultaneously. This is accomplished by the following steps:    1) Fabricate MEMS devices on a device wafer    2) Form sealing rings at the periphery of each die on the device wafer, where the sealing ring comprises a layer of silicon nitride (for electrically isolating the underlying electrical leads) followed by a solder comprising a 1st layer of titanium, a 2nd layer of palladium, and a 3rd layer of gold.    3) Similarly form sealing rings on the lid wafer.    4) The lid wafer and device wafer are aligned to each other and evacuated.    5) The wafers are heat treated to form a seal.Note that U.S. Pat. No. 6,479,320 describes the vacuum sealing of a device wafer to a lid wafer, where the MEMS devices are disposed on the device wafer.
A preferred sealing method is glass frit sealing because it forms a leak-free seal over non-planar surfaces. Glass frit compositions are well known in the art. Generally a glass frit composition comprises a glass powder, a solvent, a binder, and optionally other additives. Suitable glass powders include PbO, B2O3, silica (SiO2), alumina (Al2O3), and others. Acrylics may be used as binders. In a conventional method of sealing 2 substrates, glass frit compositions are coated at the desired bond line on one or both substrates. Methods for coating the glass frit composition include deposition from a nozzle dispenser, screen printing, tape casting, molding, and extrusion. The formulation of the glass frit composition is at least partially dependent upon the desired width and thickness of the bond line.
U.S. Pat. No. 6,583,079 describes glass frit compositions that can be sealed at relatively low temperatures of 410 to 430° C. with relatively short curing times of 5 to 20 minutes. Glass powders according to U.S. Pat. No. 6,583,079 have glass transition temperatures ranging from 296 to 321° C., and softening temperatures ranging from 338 to 398 ° C. The glass powders essentially consist of 75-90% PbO, 7-20% B2O3, 0-8% ZnO, 0-5% SiO2, and 0.1-8% Al2O3+Fe2O3.
U.S. Pat. No. 6,537,892 discloses a glass frit sealing process for MEMS devices such as accelerometers, sensors, and actuators. The process relates to the formation of a seal between a device wafer containing MEMS devices and a lid wafer. Preferred methods of curing the glass frit composition are described. There are 2 important features to this invention. Firstly, the glass frit composition contains a particular filler material that establishes a stand-off distance between the 2 wafers, where the filler material has a higher melting point than the glass frit. Secondly, the wafers are provided with recessed areas adjacent bond areas for accommodating excess glass frit material. The 2nd innovation is useful for limiting the width of the bonding line. Limiting the width of the bonding line is important when the bonding line is being formed on a high cost, device quality wafer.
Typically, an exhaust tube is placed at the periphery of the substrate so that it crosses the bonding line. Initially, there is a 1st heat treatment to remove the solvent and binder. The temperature of the 1st heat treatment may be in the range of about 100° C., to 300° C., i.e. temperatures that are sufficient to vaporize the binder and solvent but do not melt the glass powder. The substrates are aligned and are heated to melt the glass frit to form a seal around the bonding line and the exhaust pipe. The assembly is evacuated through the exhaust pipe, and when the evacuation is complete, the exhaust pipe is sealed. In an alternative method, an evacuation pipe is sealed to the outer surface of the rear substrate using frit glass. Such a method is described, for example, in U.S. Pat. No. 6,407,501, which describes a sealing method for a plasma display panel (PDP).
Sealing methods that do not use exhaust pipes have also been disclosed. The elimination of the exhaust pipe reduces manufacturing steps and makes more efficient use of the available space for the electronic device. U.S. Pat. No. 6,129,603 discloses a sealing method for a field emission display using a low temperature glass frit. A glass frit with a glass transition temperature of 200 to 250° C. is formed by mixing 2% to 4% Q-Pac organic compound with NEG (Nippon Electric Glass) low temperature glass. The glass frit composition is deposited along the bonding line on one substrate and the 2 substrates are assembled. The assembly is evacuated in a vacuum oven and then heated to <300° C. to melt the glass frit and form a seal.
Another sealing method for field emission displays without using exhaust pipes is disclosed by U.S. Pat. No. 5,997,378. The preferred glass frit is LS-1014 from Nippon Electric Glass. In this method, a glass frit composition is deposited along the bonding line. In addition, compressible protrusions of glass frit are also deposited along the bonding line. In a preferred embodiment, the compressible protrusions are about 250 microns tall and are located at 25 mm intervals. The space between the compressible protrusions act as high conductance exhaust channels during the evacuation step. After the evacuation step, the glass frit is melted in a high temperature step and the seal is formed. The evacuated chamber also includes 2 strip of getter material (ST-707 getter strip from SAES), located along the edge of the display. Metallic particles deposited on the metal foil become reactive when heated. The getter functions to decrease the pressure within the sealed space throughout the lifetime of the display. It was found that the getter was activated above 375° C.
It is known that micromirrors are sensitive to dust, particles, gases, moisture, and other environmental factors. Conventionally, electrical connections to micromirror arrays are made by wire bonding. In prior art devices where the micromirror and addressing circuitry are on the same substrate (e.g. U.S. Pat. No. 4,662,746 and U.S. Pat. No. 5,583,688), it would be desirable to form a protective layer on the micromirror array while wire bonds are formed at the periphery of the die. However, since it is not possible to remove the protective layer after the wire bonding, wire bonding must be carried out with neighboring micromirrors unprotected.
In micromirror devices where the CMOS and micromirrors are on separate substrates (e.g. U.S. Pat. No. 5,835,256), the micromirrors may be protected by sealing the 2 substrates before performing the wire bond. However, as discussed above, there are other manufacturing problems that arise from placing the CMOS circuitry and micromirrors on separate substrates.
U.S. Pat. No. 6,507,082 provides a flip-chip assembly method for devices in which the CMOS circuitry and micromirrors are on the same side of the same substrate. Furthermore, the micromirrors are protected in a protective layer during the flip-chip assembly. In summary, the method outlined in U.S. Pat. No. 6,507,082 is as follows:    1) Form micromirror arrays and addressing circuits on a substrate;    2) Form a protective layer on the substrate and pattern it such that the micromirror arrays are protected and metallic pads are exposed;    3) Deposit solder balls on the metallic pads;    4) Singulate the chips;    5) Flip-chip assemble a chip into the opening of a ceramic substrate;    6) Underfill the gaps between the solder joints with a polymeric encapsulant;    7) Remove the protective layer from the micromirror array; and    8) Attach a lid to the substrate for sealing the package.This method is an improvement in that flip-chip assembly is used and the micromirror array is protected during assembly. However, a limitation is that although the package is sealed, it is not under vacuum. It should be noted that the interface region between the chip and the package contains both the polymeric encapsulant and the solder ball array. This interface is not intended to maintain a vacuum, and it is not the intention of the patent to provide a vacuum interior.